UIC Secure and Trustworthy Computer Hardware Design
ECE 459/559 – Secure and Trustworthy Computer Hardware Design Final Exam Spring 2024 Due on Wednesday, May 15, 2024, by 6 pm through Canvas Name________________________________ There are 9 problems in this exam, and it is 4 pages. There are 50 points total. Problem 1: Multiple Choices (12 Points) 1) Side-channel attacks are defined by any of the following except: a) Measurements of electro-magnetic radiation from the chip b) Measurements of the digital input-output (I/O) behavior of the chip c) Measurements of the timing of various computations within the chip d) Correlation of the power supply transient signals of the chip to power models. 2) Simple power analysis (SPA) countermeasures include all of the following except: a) Obfuscating logic circuits using custom ASIC designs. b) Reversing the operations carried out by encryption algorithms. c) Removing conditional branch dependencies that use secret data in cryptosystems. d) Recoding microcode used by microprocessors to make them nearly equal in terms of power consumption. 3) Correlation power analysis (CPA) usually leverages which hypothetical power model: a) The Hamming weights of each possible output value (e.g. SBOX). b) Separate the traces into two groups of binary 1’s and 0’s based on SBOX output. c) Mean of the known correct key traces as a mechanism to reduce uncertainty. d) Data from a datasheet of typical power consumption for the CPU of the device. 4) Differential power analysis (DPA) creates two groups of power traces based on which of the following: a) The binary value of the target bit after the SBOX from a set of simulated plaintexts. b) The value of the key guess being correct or not correct. c) The behavior observed in the power trace waveforms. d) The difference in the total of two power trace waveforms. 5) IP piracy refers to (Select all that apply): a) Stealing data and secrets from chips such as manufacturer keys b) Reverse engineering designs and stealing design information c) Inserting trojans to leak critical information d) Stealing chips from physical foundries 6) A truly strong PUF has (Select all that apply): a) A large CRP space that is resilient to machine learning attacks b) A small source of entropy with a large CRP space c) A large source of entropy with a small CRP space d) A small CRP space that is resilient to machine learning attacks 7) Which of the following are true about Trojan Detection Approaches (Select all that apply): a) Exhaustive testing for trojans is a good option for large circuits (such as 64-bit adders) b) Detection of trojans can only be done before a chip is “taped” out and sent. c) Side-channel analysis is considered a “Non-Destructive” or “Passive” approach. d) “Destructive Approaches” to detecting trojans tend to be expensive and time consuming. 8) The most important statistical metrics associated with PUFs include all of the following except: a) Design Complexity b) Uniformity c) Uniqueness d) Reliability 9) Challenging a PUF refers to (Select all that apply): a) Applying analog stimuli to obtain an analog response from the PUF. b) Applying digital stimuli to obtain a valid response from the PUF. c) Altering temperature conditions to determine if the PUF produces random behavior. d) Applying plaintext/secret inputs to obtain an encrypted ciphertext from the PUF. 10) Which statements are true about Dual rail precharge (DRP) logic styles (Select all that apply): a) The gates operate in two phases: precharge and evaluation b) The circuit computes a differential logic function which adds noise c) True and complimentary wires are used to define connections between logic gates and the circuit d) The logic gates are defined using two separate power supplies which confuses the adversary about which power rail is actually being used 11) Which of the statements are true about voltage glitching using ChipWhisperer (Select all that apply): a) “Repeat” determines how many times it repeats glitches, where “ext_offset” is how long to wait between glitches. b) “Repeat” determines the duration of the glitch, where “ext_offset” is the offset of when the glitch begins. c) Voltage glitching is where you inject additional/over voltage, disrupting a chip. d) Voltage glitching is where you ground the supply voltage briefly, disrupting a chip. 12) PRESENT contains all of the following steps/components, except: a) 4-bit Substitution Box b) Permutation Layer c) Round Key Schedule d) Shift Rows Problem 2: True/False (3 Points) 1) All PUFs are resilient against machine learning attacks. 2) Strong PUFs’ number of CRPs generally grow exponentially as a function of size. 3) Differential Power Analysis (DPA) attacks find the Pearson Coefficient between the covariance of a power model and the acquired power traces. Short Response Questions (15 Points Total): Problem 3. What are the Spectre and Meltdown vulnerabilities? What technologies/features are these vulnerabilities exploiting? What are attacks exploiting them capable of? (5 points) Problem 4. What is a hardware trojan? Write an example of a silicon back door and a silicon time bomb in context of hardware trojans. (3 points) Problem 5. What is the difference between IP Trust and IP Security? (2 Points) Problem 6. What are voltage glitching (or crowbar) attacks? What are the desired effects of an injected glitch attack? Give an example of a likely target for a glitch attack. (3 Points) Problem 7. What is the Sensitivity Metric in Trojan Detection? Should sensitivity be close to 1% for effective Trojan detection. (2 Points) Problem 8. (10 Points) Use the following values (in hexadecimal notation): plaintext = 3003 4004 5005 6006, key = BBBB 4444 6666 FFFF C0C0. (a) Calculate the state of PRESENT-80 after the execution of one round. (b) Now calculate the round key for the second round. Problem 9. Write the Boolean equations implemented by the following two CMOS logic (10 points). (a) (b)
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