Solution to the question in the file with explanation

CPEG-510/312: Computer Architecture/Organization, Spring 2024, Homework #2. Name: _____________________________ Student ID: ___________________ 1.(20’) MIPS Assembly Language Programming: Write MIPS assembly code (implement it as a function) to reverse the bits in a register. Use as few instructions as possible. Assume the register of interest is $t3. 2. (10’) Floating Point Computation: 1). Write down the binary representation of the decimal number 63.25 assuming the IEEE 754 single precision format. 2). Write down the binary representation of the decimal number 63.25 assuming the IEEE 754 double precision format. 3. (30’) Floating Point Computation: 1). IEEE 754-2008 contains a half precision that is only 16 bits wide. The left most bit is still the sign bit, the exponent is 5 bits wide and has a bias of 15, and the mantissa is 10 bits long. A hidden 1 is assumed. Write down the bit pattern to represent 1.5625× 10-1 assuming a version of this format, which uses an excess-16 format to store the exponent. Comment on how the range and accuracy of this 16-bit floating point format compares to the single precision IEEE 754 standard. 2). Calculate the sum of 2.6125 × 101 and 4.150390625 × 10-1 by hand, assuming A and B are stored in the 16-bit half precision described in previous question. Assume 1 guard, 1 round bit, and 1 sticky bit, and round to the nearest even. Show all the steps. 4.(20’) Combinational Circuit Design: A circuit has four inputs and two outputs. The inputs Α3:0 represent a number from 0 to 15. Output P should be TRUE if the number is prime (0 and 1 are not prime, but 2, 3, 5, and so on, are prime). The truth table of the circuit is shown in Figure 1. 1). Based on the truth table, find the Boolean function of P as function of A[3], A[2], A[1], A[0] using SoP (Sum-of-Product) format. 2). Use Karnaugh map to find simplified Boolean equation of P=? 3). Sketch the gate-level implementation of the circuit. Figure 1. Truth table of the combinational circuit (prime number finder) 1 5.(20’) Sequential Circuit Design: The State Transition Graph (STG) of a sequence detector (Mealy machine) is shown in Figure 2. It takes one-bit input X, and set output Z=1 whenever the input pattern sequence of “1101” or “1110” is detected, otherwise output Z=0. Overlapping sequences are allowed. 1). Assume 3 D flip-flops (rising-edge triggered) are used to represent all the states, and the following state assignments are used: S0=Q2Q1Q0=000; S1=Q2Q1Q0=001; S2=Q2Q1Q0=010; S3=Q2Q1Q0=100, S4=Q2Q1Q0=101. Construct the binary state transition table with excitation table based on D flip-flops. 2). Based on binary state transition table, extract Karnaugh maps for each bit of the next states and output (i.e. Q2’ (D2), Q1’ (=D1), Q0’ (=D0) of flip-flop inputs and Z) as functions of current states and inputs (Q2, Q1, Q0, X). Derive the most simplified Boolean equations for D2, D1, D0 and Z=? 3). Based on the simplified Boolean equations you found, implement the complete sequence detector with logic gates and D flip-flops. Figure 2. State Transition Graph (STG) of a sequence detector (Mealy machine) Due: 02/18/2024 (Sunday) online in Canvas. 2