Verilog codes
ECE459/559 Lab 1: Introduction to Verilog Objective: – Understand the differences between structural and behavioral Verilog – Understand the basic syntax and thought processes of Verilog – Create simple testbenches and analyze waveforms/outputs You may find this link useful: https://www.chipverify.com/verilog/verilog-in-a-nutshell Part 1: a) Design a simple 1-bit full adder using structural Verilog. This means construct it using ANDs, ORs, XORs, etc. A reference for what a physical adder looks like is shown below. Remember that a full adder is one that takes a carry in input from the previous adder (the Carry out goes to the next adder’s Cin input). Hint: While it is possible to write this with a single assign statement, we want a structural design using Boolean gates in this part. Remember that gates in Verilog look a lot like OOP (in a way, it is: module instantiation), and this syntax will be how you instantiate modules in the future (i.e., problem 1b). b) Create a 4-bit full adder using the 1-bit full adder you created in part 1a. You should instantiate the 1-bit adder and connect the relevant parts using wires, inputs, outputs, etc. Remember that the first adder’s Cin (carry in) is most likely fed a value of 1’b0. c) Design a simple test bench that tests some (or all) inputs of the 4-bit adder to verify that it is working. This testbench module should be a separate module from the adder; as in, there should be a “module testbench;” that instantiates the 4-bit adder and gives it stimuli. Part 2: a) Use behavioral Verilog to generate an unsigned 8-bit saturation full adder. A saturated adder will perform the addition but will saturate the output if integer overflow occurs. For example, the output will be assigned 255 (max of 8 bit integer) if the addition between A and B go over, such as if A+B > 255 then C
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